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#define | ___APIC_H 0 |
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#define | APIC_MSR_ADDRESS 0x1B |
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#define | APIC_MSR_ENABLE_APIC 0x800UL |
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#define | APIC_MSR_ENABLE_X2APIC 0x400UL |
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#define | APIC_REGISTER_OFFSET_ID 0x20 |
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#define | APIC_REGISTER_OFFSET_VERSION 0x30 |
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#define | APIC_REGISTER_OFFSET_DFR 0xE0 |
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#define | APIC_REGISTER_OFFSET_SPURIOUS_INTERRUPT 0xF0 |
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#define | APIC_REGISTER_OFFSET_EOI 0xB0 |
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#define | APIC_REGISTER_OFFSET_ISR0 0x100 |
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#define | APIC_REGISTER_OFFSET_TIMER_LVT 0x320 |
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#define | APIC_REGISTER_OFFSET_TERMAL_SENSOR_LVT 0x330 |
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#define | APIC_REGISTER_OFFSET_PERF_COUNTER_LVT 0x340 |
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#define | APIC_REGISTER_OFFSET_LINT0_LVT 0x350 |
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#define | APIC_REGISTER_OFFSET_LINT1_LVT 0x360 |
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#define | APIC_REGISTER_OFFSET_ERROR_LVT 0x370 |
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#define | APIC_REGISTER_OFFSET_TIMER_INITIAL_VALUE 0x380 |
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#define | APIC_REGISTER_OFFSET_TIMER_CURRENT_VALUE 0x390 |
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#define | APIC_REGISTER_OFFSET_TIMER_DIVIDER 0x3E0 |
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#define | APIC_REGISTER_OFFSET_ISR0 0x100 |
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#define | APIC_REGISTER_OFFSET_ISR1 0x110 |
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#define | APIC_REGISTER_OFFSET_ISR2 0x120 |
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#define | APIC_REGISTER_OFFSET_ISR3 0x130 |
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#define | APIC_REGISTER_OFFSET_ISR4 0x140 |
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#define | APIC_REGISTER_OFFSET_ISR5 0x150 |
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#define | APIC_REGISTER_OFFSET_ISR6 0x160 |
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#define | APIC_REGISTER_OFFSET_ISR7 0x170 |
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#define | APIC_REGISTER_OFFSET_IRR0 0x200 |
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#define | APIC_REGISTER_OFFSET_IRR1 0x210 |
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#define | APIC_REGISTER_OFFSET_IRR2 0x220 |
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#define | APIC_REGISTER_OFFSET_IRR3 0x230 |
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#define | APIC_REGISTER_OFFSET_IRR4 0x240 |
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#define | APIC_REGISTER_OFFSET_IRR5 0x250 |
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#define | APIC_REGISTER_OFFSET_IRR6 0x260 |
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#define | APIC_REGISTER_OFFSET_IRR7 0x270 |
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#define | APIC_REGISTER_OFFSET_ICR_LOW 0x300 |
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#define | APIC_REGISTER_OFFSET_ICR_HIGH 0x310 |
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#define | APIC_X2APIC_MSR_APICID 0x802 |
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#define | APIC_X2APIC_MSR_VERSION 0x803 |
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#define | APIC_X2APIC_MSR_TPR 0x808 |
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#define | APIC_X2APIC_MSR_PPR 0x80A |
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#define | APIC_X2APIC_MSR_EOI 0x80B |
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#define | APIC_X2APIC_MSR_LDR 0x80D |
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#define | APIC_X2APIC_MSR_SIVR 0x80F |
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#define | APIC_X2APIC_MSR_ISR0 0x810 |
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#define | APIC_X2APIC_MSR_ISR1 0x811 |
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#define | APIC_X2APIC_MSR_ISR2 0x812 |
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#define | APIC_X2APIC_MSR_ISR3 0x813 |
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#define | APIC_X2APIC_MSR_ISR4 0x814 |
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#define | APIC_X2APIC_MSR_ISR5 0x815 |
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#define | APIC_X2APIC_MSR_ISR6 0x816 |
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#define | APIC_X2APIC_MSR_ISR7 0x817 |
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#define | APIC_X2APIC_MSR_TMR0 0x818 |
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#define | APIC_X2APIC_MSR_TMR1 0x819 |
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#define | APIC_X2APIC_MSR_TMR2 0x81A |
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#define | APIC_X2APIC_MSR_TMR3 0x81B |
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#define | APIC_X2APIC_MSR_TMR4 0x81C |
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#define | APIC_X2APIC_MSR_TMR5 0x81D |
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#define | APIC_X2APIC_MSR_TMR6 0x81E |
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#define | APIC_X2APIC_MSR_TMR7 0x81F |
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#define | APIC_X2APIC_MSR_IRR0 0x820 |
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#define | APIC_X2APIC_MSR_IRR1 0x821 |
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#define | APIC_X2APIC_MSR_IRR2 0x822 |
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#define | APIC_X2APIC_MSR_IRR3 0x823 |
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#define | APIC_X2APIC_MSR_IRR4 0x824 |
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#define | APIC_X2APIC_MSR_IRR5 0x825 |
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#define | APIC_X2APIC_MSR_IRR6 0x826 |
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#define | APIC_X2APIC_MSR_IRR7 0x827 |
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#define | APIC_X2APIC_MSR_ESR 0x828 |
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#define | APIC_X2APIC_MSR_LVT_CMCI 0x82F |
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#define | APIC_X2APIC_MSR_ICR 0x830 |
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#define | APIC_X2APIC_MSR_LVT_TIMER 0x832 |
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#define | APIC_X2APIC_MSR_LVT_THERMAL 0x833 |
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#define | APIC_X2APIC_MSR_LVT_PMI 0x834 |
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#define | APIC_X2APIC_MSR_LVT_LINT0 0x835 |
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#define | APIC_X2APIC_MSR_LVT_LINT1 0x836 |
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#define | APIC_X2APIC_MSR_LVT_ERROR 0x837 |
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#define | APIC_X2APIC_MSR_TIMER_INITIAL_VALUE 0x838 |
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#define | APIC_X2APIC_MSR_TIMER_CURRENT_VALUE 0x839 |
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#define | APIC_X2APIC_MSR_TIMER_DIVIDER 0x83E |
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#define | APIC_X2APIC_MSR_SELF_IPI 0x83F |
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#define | APIC_X2APIC_MSR_EXTENDED_APIC_CONTROL 0x841 |
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#define | APIC_X2APIC_MSR_SEOI 0x842 |
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#define | APIC_ICR_DESTINATION_MODE_PHYSICAL (0 << 11) |
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#define | APIC_ICR_DESTINATION_MODE_LOGICAL (1 << 11) |
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#define | APIC_ICR_DELIVERY_MODE_FIXED (0 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_LOWEST_PRIORITY (1 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_SMI (2 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_NMI (4 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_INIT (5 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_STARTUP (6 << 8) |
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#define | APIC_ICR_DELIVERY_MODE_EXTERNAL_INT (7 << 8) |
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#define | APIC_ICR_DELIVERY_STATUS_IDLE (0 << 12) |
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#define | APIC_ICR_DELIVERY_STATUS_SEND_PENDING (1 << 12) |
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#define | APIC_ICR_LEVEL_ASSERT (1 << 14) |
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#define | APIC_ICR_LEVEL_DEASSERT (0 << 14) |
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#define | APIC_ICR_TRIGGER_MODE_EDGE (0 << 15) |
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#define | APIC_ICR_TRIGGER_MODE_LEVEL (1 << 15) |
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#define | APIC_ICR_DESTINATION_SHORTHAND_NONE (0 << 18) |
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#define | APIC_ICR_DESTINATION_SHORTHAND_SELF (1 << 18) |
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#define | APIC_ICR_DESTINATION_SHORTHAND_ALL (2 << 18) |
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#define | APIC_ICR_DESTINATION_SHORTHAND_ALL_BUT_SELF (3 << 18) |
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#define | APIC_ICR_DESTINATION_SHIFT 24 |
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#define | APIC_IOAPIC_REGISTER_IDENTIFICATION 0x00 |
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#define | APIC_IOAPIC_REGISTER_VERSION 0x01 |
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#define | APIC_IOAPIC_REGISTER_ARBITRATION 0x02 |
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#define | APIC_IOAPIC_REGISTER_IRQ_BASE 0x10 |
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#define | APIC_IOAPIC_DELIVERY_MODE_FIXED (0 << 8) |
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#define | APIC_IOAPIC_DELIVERY_MODE_LOWEST_PRIORITY (1 << 8) |
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#define | APIC_IOAPIC_DELIVERY_MODE_SMI (2 << 8) |
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#define | APIC_IOAPIC_DELIVERY_MODE_NMI (4 << 8) |
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#define | APIC_IOAPIC_DELIVERY_MODE_INIT (5 << 8) |
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#define | APIC_IOAPIC_DELIVERY_MODE_EXTERNAL_INT (7 << 8) |
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#define | APIC_IOAPIC_DESTINATION_MODE_PHYSICAL (0 << 11) |
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#define | APIC_IOAPIC_DESTINATION_MODE_LOGICAL (1 << 11) |
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#define | APIC_IOAPIC_DELIVERY_STATUS_RELAX (0 << 12) |
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#define | APIC_IOAPIC_DELIVERY_STATUS_WAITING (1 << 12) |
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#define | APIC_IOAPIC_PIN_POLARITY_ACTIVE_HIGH (0 << 13) |
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#define | APIC_IOAPIC_PIN_POLARITY_ACTIVE_LOW (1 << 13) |
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#define | APIC_IOAPIC_TRIGGER_MODE_EDGE (0 << 15) |
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#define | APIC_IOAPIC_TRIGGER_MODE_LEVEL (1 << 15) |
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#define | APIC_IOAPIC_INTERRUPT_ENABLED (0 << 16) |
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#define | APIC_IOAPIC_INTERRUPT_DISABLED (1 << 16) |
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#define | APIC_INTERRUPT_ENABLED APIC_IOAPIC_INTERRUPT_ENABLED |
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#define | APIC_INTERRUPT_DISABLED APIC_IOAPIC_INTERRUPT_DISABLED |
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#define | APIC_TIMER_ONESHOT (0 << 17) |
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#define | APIC_TIMER_PERIODIC (1 << 17) |
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#define | APIC_TIMER_TSC_DEADLINE (2 << 17) |
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#define | APIC_IOAPIC_MAX_REDIRECTION_ENTRY(r) |
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#define | apic_ioapic_enable_irq(irq) |
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#define | apic_ioapic_disable_irq(irq) |
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apic and ioapic interface
This work is licensed under TURNSTONE OS Public License. Please read and understand latest version of Licence.